Introduction

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System Control Block (SCB): What It Does

The System Control Block (SCB) is a group of registers inside the Cortex-M System Control Space (SCS, base address 0xE000E000). It is the primary firmware interface for system-level processor control — everything from enabling configurable fault handlers to triggering a software reset. The SCB is defined by ARM and is identical across all Cortex-M3 and Cortex-M4 implementations.

What the SCB registers collectively let you do

• Enable fault handlers — activate UsageFault, BusFault, and MemManage exceptions (disabled by default; all escalate to HardFault until enabled)
• Get pending status of fault exceptions — determine which configurable fault is waiting to be handled even if it is currently masked
• Trap divide-by-zero and unaligned access — enable automatic UsageFault on integer division by zero (CCR.DIV_0_TRP) or any unaligned access (CCR.UNALIGN_TRP)
• Control sleep and wake-up settings — configure SLEEPDEEP, SLEEPONEXIT, SEVONPEND for power management
• Configure priority of system exceptions — assign preemption priorities to SVC, PendSV, SysTick, MemManage, BusFault, UsageFault
• SysTick timer control and status — start/stop the 24-bit countdown, select clock source, enable overflow interrupt

Default System Exception States

After reset, not all system exceptions are active. The following table shows the out-of-reset state of every Cortex-M system exception. Understanding these defaults prevents common bugs where firmware assumes an exception is active when it isn’t, or disables one that is already running.

/* Enable all three configurable faults at startup */
void enable_configurable_faults(void)
{
    SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk   /* bit 18: UsageFault  */
               |  SCB_SHCSR_BUSFAULTENA_Msk    /* bit 17: BusFault    */
               |  SCB_SHCSR_MEMFAULTENA_Msk;   /* bit 16: MemManage   */
}

/* Enable divide-by-zero and unaligned trapping */
void enable_usage_traps(void)
{
    SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk    /* bit 4: trap div/0 as UsageFault */
             |  SCB_CCR_UNALIGN_TRP_Msk; /* bit 3: trap unaligned access     */
}

Cortex-M4 Processor Internal Block Diagram

Understanding the internal structure of the Cortex-M4 processor shows how the NVIC, SCB, bus interfaces, and debug components connect. Every block communicates through the Bus Matrix — the central crossbar that allows multiple masters to simultaneously access different slaves.

ICSR — Interrupt Control and State Register

The Interrupt Control and State Register (ICSR) at address 0xE000ED04 is the primary software interface for querying and controlling the exception state machine. It exposes which exception is currently active, which is pending, and provides the software write-bits to trigger PendSV and NMI via firmware.

Triggering PendSV from an ISR (RTOS context switch)

/* In FreeRTOS, the SysTick handler triggers a PendSV to perform context switching.
   PendSV is set to the lowest priority so it runs after all other ISRs complete. */

void SysTick_Handler(void)
{
    /* Increment tick count */
    xTaskIncrementTick();

    /* Request context switch by pending PendSV.
       PendSV will fire after this ISR exits (tail-chaining or after all higher-prio ISRs). */
    SCB->ICSR = SCB_ICSR_PENDSVSET_Msk;   /* write 1 to bit 28 */

    /* Direct register access equivalent: */
    /* *((volatile uint32_t *)0xE000ED04) |= (1U << 28); */
}

/* PendSV_Handler performs the actual context switch */
__attribute__((naked)) void PendSV_Handler(void)
{
    __asm volatile (
        "MRS   R0, PSP          \n\t"   /* get current task's PSP */
        "STMDB R0!, {R4-R11}    \n\t"  /* save callee-saved regs */
        /* ... save R0 to current TCB, load next TCB, restore regs ... */
        "MSR   PSP, R0          \n\t"   /* restore next task's PSP */
        "BX    LR               \n\t"   /* exception return */
    );
}

Reading which exception is active

/* Read VECTACTIVE to determine current exception context */
uint32_t current_exception(void)
{
    return SCB->ICSR & 0x1FFU;   /* bits 8:0 = VECTACTIVE */
}

bool in_thread_mode(void)
{
    return current_exception() == 0;
}

bool in_handler_mode(void)
{
    return current_exception() != 0;
}

/* Example: find the highest-priority pending exception number */
uint32_t pending_exception(void)
{
    return (SCB->ICSR >> 12) & 0x1FFU;  /* VECTPENDING bits 20:12 */
}

SHCSR — System Handler Control and State Register

The System Handler Control and State Register (SHCSR) at 0xE000ED24 serves a dual role: it enables the three configurable fault exceptions (MemManage, BusFault, UsageFault) and exposes real-time active/pending status for all system exception handlers.

Using SHCSR in a fault diagnostic handler

/* Read SHCSR at the start of HardFault_Handler to understand the escalation source */
void HardFault_Handler(void)
{
    uint32_t shcsr = SCB->SHCSR;
    uint32_t hfsr  = SCB->HFSR;
    uint32_t cfsr  = SCB->CFSR;   /* combined MMFSR + BFSR + UFSR */

    if (hfsr & SCB_HFSR_FORCED_Msk) {
        /* Configurable fault escalated to HardFault */
        if (cfsr & 0xFFFF0000U) {
            /* Usage fault bits in CFSR[31:16] */
            if (cfsr & SCB_CFSR_DIVBYZERO_Msk) { /* handle div-by-zero */ }
            if (cfsr & SCB_CFSR_UNDEFINSTR_Msk) { /* undefined instruction */ }
        }
        if (cfsr & 0x0000FF00U) {
            /* Bus fault bits in CFSR[15:8] */
            if (cfsr & SCB_CFSR_BFARVALID_Msk) {
                volatile uint32_t bfar = SCB->BFAR;  /* address of faulting access */
                (void)bfar;
            }
        }
        if (cfsr & 0x000000FFU) {
            /* MemManage bits in CFSR[7:0] */
            if (cfsr & SCB_CFSR_MMARVALID_Msk) {
                volatile uint32_t mmfar = SCB->MMFAR;  /* violation address */
                (void)mmfar;
            }
        }
    }

    if (hfsr & SCB_HFSR_VECTTBL_Msk) {
        /* Vector table read error during exception entry */
    }

    while (1);   /* spin — or trigger a system reset */
}

Exercise: Enabling and Pending USART3 Interrupt

This exercise walks through the complete path from a peripheral event to ISR execution, using USART3 on STM32F411 as the example. USART3 is connected to the NVIC on IRQ line 39.

Finding the IRQ number for USART3

IRQ numbers are vendor-specific — defined by the MCU manufacturer, not by ARM. You find them in the device header file or the reference manual’s vector table section. For STM32F4 series:

/* From stm32f411xe.h (CMSIS device header) */
typedef enum {
    /* Cortex-M system exceptions (negative numbers) */
    NonMaskableInt_IRQn     = -14,
    HardFault_IRQn          = -13,
    MemoryManagement_IRQn   = -12,
    BusFault_IRQn           = -11,
    UsageFault_IRQn         = -10,
    SVCall_IRQn             = -5,
    DebugMonitor_IRQn       = -4,
    PendSV_IRQn             = -2,
    SysTick_IRQn            = -1,

    /* STM32F411 peripheral IRQs */
    WWDG_IRQn               = 0,
    /* ... */
    USART1_IRQn             = 37,
    USART2_IRQn             = 38,
    USART3_IRQn             = 39,   /* ← USART3 is IRQ 39 */
    /* ... */
} IRQn_Type;

Calculating the NVIC register bit for IRQ 39

NVIC ISER/ICER/ISPR/ICPR registers are 32-bit wide. Each register covers 32 IRQs: ISER[0] covers IRQ0–31, ISER[1] covers IRQ32–63, etc.

/* IRQ 39 → register index = 39 / 32 = 1 → ISER[1]
              bit position  = 39 % 32 = 7 → bit 7 of ISER[1] */

/* Direct register access (without CMSIS): */
#define NVIC_ISER1   (*(volatile uint32_t *)0xE000E104U)
#define NVIC_ISPR1   (*(volatile uint32_t *)0xE000E204U)
#define NVIC_IPR9    (*(volatile uint32_t *)0xE000E424U)  /* IPR byte for IRQ39 */

/* Enable IRQ39 */
NVIC_ISER1 = (1U << 7);        /* bit 7 of ISER[1] */

/* Set priority = 5 (using top 4 bits → value = 5 << 4 = 0x50) */
/* IPR registers: 4 IRQs per 32-bit word; IRQ39 is byte 3 of IPR9 */
NVIC_IPR9 = (NVIC_IPR9 & ~(0xFFU << 24)) | (0x50U << 24);

/* Software-pend IRQ39 (simulate USART3 interrupt firing) */
NVIC_ISPR1 = (1U << 7);

/* Using CMSIS (preferred): */
NVIC_SetPriority(USART3_IRQn, 5);
NVIC_EnableIRQ(USART3_IRQn);

6 Steps to Configure Any MCU Peripheral Interrupt

This process applies to every peripheral interrupt on every Cortex-M based MCU. The steps always follow this order — changing the order (especially enabling the peripheral before the NVIC) can cause interrupts to fire before the handler is ready.

1

Identify the IRQ number (vendor-specific)

Look up the peripheral’s IRQ number in the MCU’s device header file or the vector table section of the reference manual. This is not standardised by ARM — USART3 is IRQ39 on STM32F4, but a completely different number on NXP or TI parts. Never hardcode IRQ numbers; always use the enumeration from the CMSIS device header.

2

Enable the IRQ in the NVIC and set priority

Write to NVIC_ISER to enable the IRQ line. Optionally set the priority in NVIC_IPR. If no priority is set, the default is 0 (highest). Always set priorities before enabling — setting priority after enabling creates a brief window where the IRQ can fire at the wrong priority.

NVIC_SetPriority(USART3_IRQn, 5);   /* set first */
NVIC_EnableIRQ(USART3_IRQn);         /* then enable */

3

Configure the peripheral to generate the interrupt

Set the interrupt-enable bit(s) in the peripheral’s own control register. For USART3: set USART_CR1.RXNEIE (receive buffer not empty interrupt enable) to trigger an interrupt whenever a byte is received. Until this step, the NVIC line is armed but the peripheral never fires it.

/* Enable USART3 receive interrupt */
USART3->CR1 |= USART_CR1_RXNEIE;   /* bit 5 in CR1 */
USART3->CR1 |= USART_CR1_UE;       /* enable USART3 */

4

Interrupt fires → NVIC pending register is set first

When USART3 issues a signal on IRQ39, the NVIC immediately sets the pending bit in NVIC_ISPR[1] bit 7. The interrupt does not immediately run the handler — it enters the pending state. This pending state persists even if the IRQ is currently disabled in the NVIC (step 2 not done yet), meaning events are not lost while the IRQ is temporarily masked.

5

NVIC runs the handler only if priority qualifies

The NVIC allows the pending IRQ to activate only if its preemption priority is numerically lower (higher priority) than the currently executing exception (or if no exception is active). If a higher-priority ISR is already running, the new IRQ stays in pending state until the higher-priority handler finishes. This is the “nested” part of NVIC.

/* Example priority check logic (hardware does this automatically):
   Currently active IRQ priority = 3
   New USART3 priority = 5 (numerically higher = lower priority)
   → USART3 stays pending until active IRQ exits */

   /* If USART3 priority = 2 (numerically lower = higher priority):
   → USART3 preempts the current ISR (tail-chain or preempt) */

6

Pending events survive IRQ disable — fire immediately on re-enable

If the peripheral generates an interrupt when the IRQ is disabled in the NVIC (ISER bit = 0), the event is still recorded in the NVIC pending register. As soon as the IRQ is re-enabled (ISER bit set to 1), the NVIC immediately evaluates the pending bit. If the priority qualifies, the ISR fires right away — without waiting for another peripheral event. This ensures no interrupts are silently dropped during critical sections.

NVIC_DisableIRQ(USART3_IRQn);
/* USART3 byte arrives here → pending bit set, but ISR does not fire */
critical_section_work();
NVIC_EnableIRQ(USART3_IRQn);
/* ↑ USART3_IRQHandler fires here immediately if priority qualifies */

Complete USART3 interrupt setup example

#include "stm32f4xx.h"

/* Step 1–3: Full USART3 receive interrupt configuration */
void usart3_irq_init(void)
{
    /* Enable clocks */
    RCC->APB1ENR |= RCC_APB1ENR_USART3EN;   /* USART3 clock */
    RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN;    /* GPIOB for TX/RX pins */

    /* Configure PB10 (TX) and PB11 (RX) as AF7 (USART3) */
    GPIOB->MODER  |=  (2U << 20) | (2U << 22);   /* alternate function mode */
    GPIOB->AFR[1] |=  (7U <<  8) | (7U << 12);   /* AF7 = USART3 */

    /* Configure USART3: 115200 baud at PCLK1 = 50 MHz */
    /* BRR = 50,000,000 / 115200 ≈ 434 = 0x1B2 */
    USART3->BRR = 0x1B2U;
    USART3->CR1 = USART_CR1_TE | USART_CR1_RE;  /* TX + RX enable, no IRQ yet */

    /* Step 1: IRQ number = USART3_IRQn = 39 (from device header) */
    /* Step 2: Configure NVIC */
    NVIC_SetPriority(USART3_IRQn, 5);
    NVIC_EnableIRQ(USART3_IRQn);

    /* Step 3: Enable RXNE interrupt in USART3, then enable USART */
    USART3->CR1 |= USART_CR1_RXNEIE | USART_CR1_UE;
    /* From this point, any received byte triggers USART3_IRQHandler */
}

/* Step 4–6 happen automatically in hardware */

/* The ISR: */
void USART3_IRQHandler(void)
{
    if (USART3->SR & USART_SR_RXNE) {
        uint8_t data = (uint8_t)(USART3->DR & 0xFFU);
        /* process received byte */
        (void)data;
    }
    /* Clear RXNE by reading DR (done above).
       If using DMA, clear DMAR bit in CR3 instead. */
}

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