Introduction

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Processor-Internal Peripheral Overview

Unlike the vendor peripherals (USART, SPI, GPIO) that ST adds to the STM32 chip, the following peripherals are part of the ARM Cortex-M processor core itself. They are identical across every Cortex-M3 and Cortex-M4 implementation — whether the chip is from ST, NXP, TI, or any other ARM licensee. Their addresses, register layouts, and behaviour are all defined by ARM and cannot be changed by the chip vendor.

NVIC — Nested Vectored Interrupt Controller

The NVIC is the heart of the Cortex-M exception system. It accepts interrupt requests from up to 240 peripheral sources, prioritises them, and signals the CPU core to take the appropriate exception. The “nested” part means the NVIC can preempt a lower-priority ISR with a higher-priority one automatically.

NVIC registers (inside SCS at 0xE000E000)

NVIC usage with CMSIS

#include "stm32f4xx.h"   /* includes CMSIS core_cm4.h */

/* Enable USART2 IRQ at priority 5 (STM32F4: 4-bit priority → value 5<<4 = 0x50) */
void nvic_setup_usart2(void)
{
    NVIC_SetPriority(USART2_IRQn, 5);   /* priority level 5 */
    NVIC_EnableIRQ(USART2_IRQn);        /* set bit in ISER */
}

/* Disable USART2 IRQ */
void nvic_disable_usart2(void)
{
    NVIC_DisableIRQ(USART2_IRQn);       /* set bit in ICER */
}

/* Software-trigger an IRQ (useful for testing or deferred work) */
void trigger_usart2_isr_software(void)
{
    NVIC_SetPendingIRQ(USART2_IRQn);    /* write to ISPR */
}

/* Direct register access (no CMSIS) — enable IRQ 38 (USART2 on STM32F4) */
#define NVIC_ISER1  (*(volatile uint32_t *)0xE000E104U)
NVIC_ISER1 = (1U << (38 - 32));   /* IRQ38 is bit 6 of ISER[1] */

Priority grouping

The 4 implemented priority bits on STM32F4 are split into preemption priority (determines nesting) and sub-priority (breaks ties between same-preemption-level IRQs). This split is configured in the SCB’s AIRCR register via the PRIGROUP field. CMSIS provides NVIC_SetPriorityGrouping() to set it.

/* Example: 3 bits preemption, 1 bit sub-priority (group 4) */
NVIC_SetPriorityGrouping(4);   /* PRIGROUP = 4 → [7:5] preempt, [4] sub */

/* IRQ with preempt=3, sub=0 */
uint32_t pri = NVIC_EncodePriority(4, 3, 0);
NVIC_SetPriority(TIM2_IRQn, pri);

SCB — System Control Block

The System Control Block (SCB) contains the configuration and status registers for the processor core — fault status, sleep control, exception prioritisation for system exceptions (HardFault, MemManage, BusFault, UsageFault, SVC, PendSV, SysTick), and the vector table offset register.

Common SCB operations

#include "core_cm4.h"   /* CMSIS */

/* 1. Software system reset */
void system_reset(void)
{
    __DSB();                    /* ensure all memory writes are complete */
    SCB->AIRCR = (0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
                  SCB_AIRCR_SYSRESETREQ_Msk;
    while (1);                  /* wait for reset */
}

/* 2. Relocate vector table to SRAM (after copying it there) */
void relocate_vtable_to_sram(void)
{
    /* Copy vector table from Flash to SRAM */
    memcpy((void *)0x20000000, (void *)0x08000000, 0x200);
    __DSB();
    SCB->VTOR = 0x20000000;     /* now uses SRAM vector table */
    __DSB();
}

/* 3. Enable configurable faults */
void enable_configurable_faults(void)
{
    SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk |   /* UsageFault */
                   SCB_SHCSR_BUSFAULTENA_Msk |   /* BusFault */
                   SCB_SHCSR_MEMFAULTENA_Msk;    /* MemManage */
}

/* 4. Read CPUID to identify the processor */
void print_cpuid(void)
{
    uint32_t cpuid = SCB->CPUID;
    uint8_t impl  = (cpuid >> 24) & 0xFF;   /* 0x41 = ARM */
    uint8_t part  = (cpuid >> 4)  & 0xFFF;  /* 0xC24 = Cortex-M4 */
    uint8_t rev   =  cpuid        & 0xF;
    /* STM32F411: impl=0x41, part=0xC24, rev=1 */
}

SysTick — System Timer

SysTick is a 24-bit countdown timer built into every Cortex-M processor. It fires the SysTick exception (exception number 15, the highest-numbered system exception) every time the counter counts from the reload value down to zero. Its primary use is as the RTOS scheduling tick — a free-running periodic interrupt that triggers the task switcher.

Configuring SysTick for a 1 ms tick (STM32F411 at 100 MHz)

/* STM32F411 core clock = 100 MHz = 100,000,000 Hz
   For 1 ms tick: reload = (100,000,000 / 1000) - 1 = 99999 */

void systick_init_1ms(void)
{
    SysTick->LOAD = 99999U;          /* reload value for 1 ms */
    SysTick->VAL  = 0U;              /* clear current value */
    SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |   /* AHB clock (not /8) */
                    SysTick_CTRL_TICKINT_Msk    |   /* enable SysTick IRQ */
                    SysTick_CTRL_ENABLE_Msk;         /* start counter */
}

/* SysTick exception handler — called every 1 ms */
volatile uint32_t g_tick_ms = 0;

void SysTick_Handler(void)
{
    g_tick_ms++;
}

/* Blocking delay using SysTick */
void delay_ms(uint32_t ms)
{
    uint32_t start = g_tick_ms;
    while ((g_tick_ms - start) < ms);
}

/* Non-blocking elapsed time */
uint32_t millis(void)
{
    return g_tick_ms;
}

MPU — Memory Protection Unit

The MPU is an optional (but universally present on Cortex-M3/M4) hardware unit that enforces access permissions on memory regions. It generates a MemManage fault when code violates its rules, making it a critical safety tool for RTOS task isolation and stack overflow detection.

MPU stack guard example

/* Configure region 7 as a no-access guard at the bottom of the stack
   to detect stack overflow — causes MemManageFault before corruption */

void mpu_set_stack_guard(uint32_t stack_bottom)
{
    /* Disable MPU before configuring */
    MPU->CTRL = 0;

    /* Region 7: 32-byte no-access region at stack_bottom */
    MPU->RNR  = 7U;
    MPU->RBAR = (stack_bottom & 0xFFFFFFE0U);   /* 32-byte aligned */
    MPU->RASR = (0b100   << 1)  |   /* SIZE = 4 → 2^(4+1) = 32 bytes */
                (0b000   << 24) |   /* AP = 000 → no access (priv or unpriv) */
                (1U      << 28) |   /* XN = 1 → no execute */
                (1U      << 0);     /* ENABLE this region */

    /* Re-enable MPU with background region for privileged code */
    __DSB();
    MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
    __ISB();
}

/* Now any PUSH that crosses into the guard zone fires MemManage_Handler
   rather than silently corrupting data below the stack. */

FPU — Floating-Point Unit (Cortex-M4F)

The Cortex-M4F includes a single-precision IEEE 754 floating-point unit. It adds 32 single-precision registers (S0–S31, also accessible as 16 double-precision D0–D15) and the FPSCR (FP Status and Control Register). The FPU must be explicitly enabled in firmware before any FP instruction executes — it is disabled after reset to save power.

Enabling the FPU

/* FPU access is controlled through the Coprocessor Access Control Register (CPACR)
   in the SCB — address 0xE000ED88
   CP10 and CP11 must both be set to 0b11 (full access) */

void fpu_enable(void)
{
    /* Set CP10 and CP11 full access */
    SCB->CPACR |= (0xFU << 20);   /* bits 23:20 → CP11 and CP10 = 11b each */
    __DSB();
    __ISB();   /* flush pipeline so next FP instruction sees the change */
}

/* GCC / STM32CubeIDE automatically calls SystemInit() which calls fpu_enable()
   if compiled with -mfpu=fpv4-sp-d16 -mfloat-abi=hard */

FPU and exception stacking

When the FPU is active and an exception fires, the hardware uses lazy stacking — it reserves space for the FP context (S0–S15, FPSCR = 17 words = 68 bytes) on the stack but does not actually write the FP registers unless the handler uses an FP instruction. This reduces interrupt latency for ISRs that don’t use floating point.

/* Total exception frame with FPU lazy stacking: */
/* 8 integer regs (32 bytes) + 1 reserved word (4 bytes) + 17 FP words (68 bytes) = 104 bytes */

/* To check if lazy stacking allocated space: */
uint32_t lspact = (FPU->FPCCR >> 0) & 1U;   /* LSPACT bit in FPCCR (0xE000EF34) */
if (lspact) {
    /* FP context is allocated but not yet saved — first FP instruction in ISR
       triggers the actual save automatically */
}

Debug Infrastructure

The Cortex-M debug system (ARM CoreSight) provides non-invasive hardware tracing, breakpoints, watchpoints, and register inspection — all accessible through standard debug ports (SWD or JTAG) without modifying the firmware.

ITM

Instrumentation Trace Macrocell: Provides a low-overhead printf-style output channel via the SWO (Single-Wire Output) pin. You write a byte to ITM->PORT[0].u8 and it appears in the debugger’s SWO viewer. Typically 50–100× faster than UART-based logging with no timing disruption.

DWT

Data Watchpoint & Trace: Contains a 32-bit free-running cycle counter (DWT_CYCCNT) that counts every processor clock cycle. Useful for profiling — read before and after a code section and subtract. Also provides up to 4 hardware data watchpoints (trigger on read/write to a specific address) without code modification.

FPB

Flash Patch & Breakpoint: Provides up to 8 hardware instruction breakpoints and 2 literal patch points. Hardware breakpoints halt the processor without any software overhead, unlike software breakpoints (BKPT instruction) that consume a word in Flash.

Using DWT_CYCCNT for microsecond profiling

/* Enable DWT cycle counter — must enable DWT first via CoreDebug */
void dwt_enable(void)
{
    CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;   /* enable DWT */
    DWT->CYCCNT = 0;                                   /* reset counter */
    DWT->CTRL  |= DWT_CTRL_CYCCNTENA_Msk;              /* start counting */
}

/* Measure execution time of a function in microseconds */
uint32_t measure_us(void (*fn)(void))
{
    uint32_t start = DWT->CYCCNT;
    fn();
    uint32_t end = DWT->CYCCNT;
    /* Divide by cycles per microsecond (= CPU freq in MHz) */
    return (end - start) / 100U;   /* 100 MHz → divide by 100 */
}

/* ITM printf via SWO */
int itm_putchar(int c)
{
    while (ITM->PORT[0].u32 == 0);    /* wait for port ready */
    ITM->PORT[0].u8 = (uint8_t)c;
    return c;
}

System Exception Numbers and Priorities

Cortex-M defines a set of system exceptions with fixed exception numbers (1–15). They are processor-internal, unlike external IRQs (numbers 16+). Their priority registers are in SHPR1–3 of the SCB, not in NVIC_IPR.

Frequently Asked Questions

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