IRQ Number Tie-Break

The priority resolution tree has three levels. The NVIC works through them in order whenever two or more interrupts are simultaneously pending:

Priority Configuration Exercise

A practical way to study how the NVIC arbitrates between priorities is to pend interrupts manually using the NVIC Set Pending Register (NVIC_ISPR) — no peripheral hardware is needed. The exercise below pends TIM2 and I2C1_EV simultaneously and observes which ISR fires first.

Setup: STM32F4 IRQ numbers

Experiment A: Same Priority

#include "stm32f4xx.h"
#include <stdio.h>

void TIM2_IRQHandler(void)
{
    printf("TIM2 ISR running\r\n");
    /* Clear the pending bit — for a manually-pended IRQ just return */
}

void I2C1_EV_IRQHandler(void)
{
    printf("I2C1_EV ISR running\r\n");
}

int main(void)
{
    /* Configure both ISRs at the same priority */
    NVIC_SetPriorityGrouping(4U);           /* all bits = pre-empt, STM32F4 */
    NVIC_SetPriority(TIM2_IRQn,     5);     /* priority 5 → 0x50 in IPR */
    NVIC_SetPriority(I2C1_EV_IRQn,  5);     /* same priority */

    /* Enable both IRQs */
    NVIC_EnableIRQ(TIM2_IRQn);
    NVIC_EnableIRQ(I2C1_EV_IRQn);

    /* Pend both at the same time */
    NVIC->ISPR[0] = (1U << 28) | (1U << 31);

    /* IRQ28 (TIM2) fires first because 28 < 31 (tie-break by IRQ number) */

    while (1) {}
}

Expected output (observe via SWO/UART):

TIM2 ISR running
I2C1_EV ISR running

Experiment B: Different Priority

    /* Give I2C1 a higher priority (lower value) */
    NVIC_SetPriority(TIM2_IRQn,    5);   /* lower urgency */
    NVIC_SetPriority(I2C1_EV_IRQn, 3);  /* higher urgency */

    /* Pend both */
    NVIC->ISPR[0] = (1U << 28) | (1U << 31);

    /* I2C1 fires first despite having a higher IRQ number */

I2C1_EV ISR running
TIM2 ISR running

Pending Interrupt Behavior

Every IRQ has two status bits in the NVIC: a pending bit (in NVIC_ISPR/ICPR) and an active bit (in NVIC_IABR). Understanding how these two bits change through an interrupt’s lifecycle is essential for writing correct ISRs and avoiding missed-interrupt bugs.

Exception Entry Sequence (7 Steps)

When the NVIC decides to take an exception, the processor executes the following sequence automatically — entirely in hardware, before the first instruction of the ISR runs:

Visualising the Stack During Entry

Exception Exit and EXC_RETURN

The ARM Cortex-M exception return mechanism does not use a normal function return address. Instead, it uses a special 32-bit value called EXC_RETURN that encodes the target mode and stack pointer to restore.

Exception Exit Steps

EXC_RETURN Values Table

Hardware generates one of three EXC_RETURN values depending on which stack was active before the exception and whether the FPU (Cortex-M4F) has live registers:

Practical Code

Reading EXC_RETURN from Inside an ISR

/* Print EXC_RETURN value from within an ISR.
 * The compiler saves LR to the stack on ISR entry (if the ISR
 * calls any sub-function). We read it via inline asm. */
void TIM2_IRQHandler(void)
{
    uint32_t exc_return;
    __asm volatile ("MOV %0, LR" : "=r" (exc_return));

    if (exc_return == 0xFFFFFFF9U) {
        /* Interrupted code was in Thread mode, using MSP */
    } else if (exc_return == 0xFFFFFFFDU) {
        /* Interrupted code was in Thread mode, using PSP (RTOS task) */
    } else if (exc_return == 0xFFFFFFF1U) {
        /* Nested exception — interrupted another handler */
    }

    /* Clear TIM2 update interrupt flag before returning */
    TIM2->SR &= ~TIM_SR_UIF;
}

Observing Active Bits

/* Check whether an IRQ is currently active (its ISR is running) */
int irq_is_active(IRQn_Type irq)
{
    if (irq < 0) return 0;   /* system exceptions not in IABR */
    uint32_t reg = (uint32_t)irq / 32U;
    uint32_t bit = (uint32_t)irq % 32U;
    return (int)((NVIC->IABR[reg] >> bit) & 1U);
}

/* Check pending bit */
int irq_is_pending(IRQn_Type irq)
{
    return (int)((NVIC->ISPR[(uint32_t)irq / 32U] >> ((uint32_t)irq % 32U)) & 1U);
}

Minimal Bare-Metal ISR Template

/* A complete bare-metal ISR for TIM2 on STM32F4.
 * Hardware stacks R0-R3, R12, LR, PC, xPSR on entry.
 * Hardware unstacks them on exit via EXC_RETURN.
 * No __attribute__((interrupt)) needed on Cortex-M. */

volatile uint32_t tim2_tick_count = 0;

void TIM2_IRQHandler(void)
{
    /* 1. Clear the peripheral interrupt flag FIRST.
     *    If you clear it last, there is a window where the flag is
     *    still set when the ISR returns, causing an immediate re-entry. */
    TIM2->SR = ~TIM_SR_UIF;   /* RC_W0 field: write 0 to clear */

    /* 2. Do the work */
    tim2_tick_count++;

    /* 3. Return: compiler emits BX LR.
     *    LR contains EXC_RETURN (e.g. 0xFFFFFFF9).
     *    Hardware unstacks and returns to interrupted code. */
}

Nested Exception — Reading Active Exception Number

/* IPSR (bits[8:0] of xPSR) holds the current exception number.
 * 0 = Thread mode, 1 = Reset, 2 = NMI, 3 = HardFault,
 * 4 = MemManage, 5 = BusFault, 6 = UsageFault,
 * 11 = SVC, 14 = PendSV, 15 = SysTick, 16+ = IRQ0+ */
uint32_t get_active_exception(void)
{
    return __get_xPSR() & 0x1FFU;   /* CMSIS */
}

/* Equivalent without CMSIS */
uint32_t get_active_exception_raw(void)
{
    uint32_t ipsr;
    __asm volatile ("MRS %0, IPSR" : "=r" (ipsr));
    return ipsr & 0x1FFU;
}

Frequently Asked Questions

Suggested Diagrams for This Lecture

• Timeline diagram: IRQ asserted → pending → entry → ISR → exit → Thread resumed
• Stack frame layout: 8 registers pushed, SP movement, new SP position
• EXC_RETURN bit-field breakdown: bits [31:4] = magic, bit[3] = FPU, bit[2] = Thread, bit[0] = PSP
• Nested ISR stack diagram: two consecutive frames on MSP
• Priority arbitration flowchart: pre-empt → sub-priority → IRQ number