1. Overview — What This Example Does

The 003_operation_modes project demonstrates the two execution modes of the ARM Cortex-M4 processor: Thread Mode and Handler Mode. It shows how software can trigger an interrupt (IRQ3) using the NVIC Software Trigger Interrupt Register (STIR), causing the processor to switch from Thread Mode to Handler Mode to execute the ISR.

The example sequence:

1. Print “In thread mode : before interrupt” (Thread Mode)
2. Enable IRQ3 in NVIC ISER0
3. Write IRQ3 to STIR → CPU immediately jumps to RTC_WKUP_IRQHandler (Handler Mode)
4. ISR prints “In handler mode : ISR”
5. ISR returns → CPU back to Thread Mode
6. Print “In thread mode : after interrupt”

2. Source Code — Full Annotated Walkthrough

#include <stdio.h>
#include <stdint.h>

/* ----------------------------------------------------------------
 * generate_interrupt() — executes in THREAD MODE
 * Demonstrates how to manually trigger an interrupt via NVIC.
 * ---------------------------------------------------------------- */
void generate_interrupt()
{
    /* STIR: Software Trigger Interrupt Register
     * Address: 0xE000EF00
     * Write the IRQ number (0–239) to trigger that interrupt in software.
     * Only accessible from privileged mode (Thread Privileged or Handler). */
    uint32_t *pSTIR  = (uint32_t*)0xE000EF00;

    /* ISER0: Interrupt Set-Enable Register 0
     * Address: 0xE000E100
     * Each bit enables one IRQ: bit N enables IRQ N (N = 0–31).
     * Must enable BEFORE writing to STIR, otherwise interrupt is pending
     * but not taken (it stays in NVIC pending state). */
    uint32_t *pISER0 = (uint32_t*)0xE000E100;

    /* Enable IRQ3 (RTC_WKUP on STM32F407) */
    *pISER0 |= (1 << 3);   /* Set bit 3 in ISER0 = enable IRQ3 */

    /* Trigger IRQ3 via software.
     * STIR bits [8:0] hold the interrupt ID.
     * We mask with 0x1FF to ensure only bits [8:0] are set. */
    *pSTIR = (3 & 0x1FF);   /* IRQ3 → triggers RTC_WKUP_IRQHandler */
}

/* ----------------------------------------------------------------
 * main() — Thread Mode
 * ---------------------------------------------------------------- */
int main(void)
{
    printf("In thread mode : before interrupt\n");

    generate_interrupt();  /* This causes an immediate mode switch */

    /* Execution resumes HERE after ISR returns */
    printf("In thread mode : after interrupt\n");

    for(;;);
}

/* ----------------------------------------------------------------
 * RTC_WKUP_IRQHandler — Handler Mode (ISR for IRQ3)
 * The processor automatically switches to Handler Mode when entering
 * any exception (including IRQs). No software action needed.
 * ---------------------------------------------------------------- */
void RTC_WKUP_IRQHandler(void)
{
    printf("In handler mode : ISR\n");
    /* Implicit return: hardware restores Thread Mode context */
}

Key Observations

• The IRQ3 vector in the vector table maps to RTC_WKUP_IRQHandler (position 3 in device IRQ table = vector table offset 3+16 = index 19, address 0x08000000 + 19×4 = 0x0800004C)
• Writing to STIR triggers the interrupt synchronously — the CPU enters the ISR before the next instruction of generate_interrupt()
• The ISR runs in Handler Mode with MSP (Main Stack Pointer) active
• Return from ISR uses a special EXC_RETURN value loaded into PC

3. ARM Cortex-M4 Processor Modes — Deep Dive

The Two Modes

XPSR — Program Status Register

The XPSR is a composite register made of three sub-registers:

uint32_t xpsr;
__asm volatile ("MRS %0, XPSR" : "=r"(xpsr));
uint8_t exception_num = xpsr & 0x1FF;   /* bits [8:0] = IPSR */
if (exception_num == 0)
    printf("Thread Mode\n");
else
    printf("Handler Mode, exception #%d\n", exception_num);

4. NVIC Registers Used

ISER — Interrupt Set-Enable Register

Base address: 0xE000E100. There are 8 ISER registers (ISER0–ISER7), each covering 32 IRQs.

To enable IRQ N: Write 1 to bit (N % 32) of ISER(N/32).

/* Generic: enable any IRQ number */
void NVIC_EnableIRQ(uint8_t irq)
{
    volatile uint32_t *ISER = (uint32_t*)0xE000E100;
    ISER[irq / 32] |= (1UL << (irq % 32));
}

/* Disable IRQ: use ICER (Interrupt Clear-Enable Register) */
void NVIC_DisableIRQ(uint8_t irq)
{
    volatile uint32_t *ICER = (uint32_t*)0xE000E180;
    ICER[irq / 32] = (1UL << (irq % 32));  /* write-to-clear */
}

STIR — Software Trigger Interrupt Register

Address: 0xE000EF00

ISPR — Interrupt Set-Pending Register

Address: 0xE000E200. Writing 1 to bit N manually sets IRQ N to pending state. The interrupt will be taken when it is enabled and priority allows.

STM32F407 IRQ Table (First 10)

5. Exception Entry Mechanism

When IRQ3 fires, the processor performs the following in hardware automatically (no software involvement):

/* What the ARM Cortex-M4 hardware does automatically on exception entry */

/* 1. STACKING — saves current context to the active stack (PSP or MSP) */
push to stack:
    R0, R1, R2, R3,    /* General purpose registers (caller-saved) */
    R12,               /* Intra-procedure-call scratch register */
    LR,                /* Link Register (return address from interrupted code) */
    PC,                /* Program Counter (address of interrupted instruction +4) */
    xPSR               /* Execution flags + IPSR + T-bit */

/* 2. Vector fetch — reads the ISR address from the vector table */
ISR_addr = *(uint32_t*)(VTOR + exception_number * 4);
/* For IRQ3: VTOR + (3+16)*4 = 0x08000000 + 19*4 = 0x0800004C */

/* 3. Mode switch — IPSR updated, T-bit checked */
IPSR = exception_number;    /* XPSR[8:0] = 19 (3+16) */
/* Processor is now in HANDLER MODE */

/* 4. LR gets EXC_RETURN value (not a normal return address!) */
LR = 0xFFFFFFF9;  /* if Thread Mode was using MSP before exception */
LR = 0xFFFFFFFD;  /* if Thread Mode was using PSP before exception */

/* 5. PC loaded from vector table → ISR begins executing */

EXC_RETURN Values

In this example, Thread Mode was using MSP (CONTROL.SPSEL=0, default after reset), so LR = 0xFFFFFFF9. When the ISR executes BX LR, the hardware sees this magic value and:

• Pops R0–R3, R12, LR, PC, xPSR from the stack
• Restores IPSR to 0 (Thread Mode)
• Resumes execution at the saved PC (instruction after the STIR write)

6. Extended Examples

Reading Current Mode in Software

#include <stdint.h>
#include <stdio.h>

typedef enum { THREAD_MODE, HANDLER_MODE } cpu_mode_t;

cpu_mode_t get_current_mode(void)
{
    uint32_t ipsr;
    __asm volatile ("MRS %0, IPSR" : "=r"(ipsr));
    return (ipsr & 0x1FF) ? HANDLER_MODE : THREAD_MODE;
}

void print_mode(void)
{
    if (get_current_mode() == THREAD_MODE)
        printf("Currently in: THREAD MODE\n");
    else
        printf("Currently in: HANDLER MODE (exception #%ld)\n",
               /* re-read IPSR */ ({uint32_t x; __asm volatile("MRS %0,IPSR":"=r"(x)); x&0x1FF;}));
}

Triggering Multiple IRQs

volatile uint32_t *ISER0 = (uint32_t*)0xE000E100;
volatile uint32_t *STIR  = (uint32_t*)0xE000EF00;

void trigger_multiple(void)
{
    /* Enable IRQ3 (RTC_WKUP), IRQ6 (EXTI0), IRQ9 (EXTI3) */
    *ISER0 |= (1<<3) | (1<<6) | (1<<9);

    /* Trigger them in sequence — each returns before next is triggered
     * because STIR triggers synchronously when priority allows */
    *STIR = 3;   /* IRQ3 fires immediately → ISR runs → return */
    *STIR = 6;   /* IRQ6 fires immediately → ISR runs → return */
    *STIR = 9;   /* IRQ9 fires immediately → ISR runs → return */
}

7. Interview Questions & Answers