What You Will Learn

Prerequisites

The struct clk_mux Wrapper

A mux clock’s hardware-specific state is a register plus enough information to turn a
parent index into the right bit pattern for that register.

struct clk_mux {
    struct clk_hw hw;
    void __iomem *reg;
    u32 *table;
    u32 mask;
    u8 shift;
    u8 flags;
    spinlock_t *lock;
};

#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)

• reg: the MMIO register used for parent selection
• table: an optional array mapping each parent index to an explicit register value
• mask/shift: used to extract or place the selector bits within reg
• flags: mux-specific behavior flags, covered next
• lock: shared spinlock protecting register access

By default, when the register’s selector field reads 0, that corresponds
to the first parent, 1 to the second, and so on — a plain sequential
mapping. The flags below exist for hardware that deviates from this default.

The Five Mux-Specific Flags

• CLK_MUX_INDEX_BIT: the register value is a power of two rather than a plain index (parent 2 maps to the value 4, not 2)
• CLK_MUX_HIWORD_MASK: uses the same hiword-mask write pattern introduced in the gate clock lecture
• CLK_MUX_INDEX_ONE: register values start counting from 1 instead of 0
• CLK_MUX_READ_ONLY: the mux is preconfigured at reset and cannot be changed at runtime
• CLK_MUX_ROUND_CLOSEST: when validating a requested rate, prefer whichever parent’s rate is closest to the target instead of the first one that fits

Registering With clk_hw_register_mux()

struct clk_hw *clk_hw_register_mux(struct device *dev, const char *name,
                                    const char * const *parent_names,
                                    u8 num_parents, unsigned long flags,
                                    void __iomem *reg, u8 shift, u8 width,
                                    u8 clk_mux_flags, spinlock_t *lock);

parent_names lists every possible parent by name, and
num_parents says how many there are — both are new here compared to
earlier single/no-parent clock types, since a mux is the first type in this chapter that
genuinely needs to describe more than one parent at registration time.

Two Different Built-In Ops, Chosen at Registration

Depending on whether CLK_MUX_READ_ONLY is set, the framework silently
assigns one of two different ops structs:

const struct clk_ops clk_mux_ops = {
    .get_parent     = clk_mux_get_parent,
    .set_parent     = clk_mux_set_parent,
    .determine_rate = clk_mux_determine_rate,
};
EXPORT_SYMBOL_GPL(clk_mux_ops);

const struct clk_ops clk_mux_ro_ops = {
    .get_parent = clk_mux_get_parent,
};
EXPORT_SYMBOL_GPL(clk_mux_ro_ops);

A read-only mux has no way to change parent at runtime, so
clk_mux_ro_ops only reports which parent is active; a normal switchable mux
gets the full clk_mux_ops, which can also switch parents and validate a
requested rate across them.

Original Demo: A Two-Parent Switchable Mux

/* ep_mux_clk_demo.c - selects between two parent clocks via a single register bit */
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/io.h>
#include <linux/spinlock.h>

static const char * const ep_mux_parents[] = { "ep_bus_clk", "ep_ext_osc" };

struct ep_mux_demo_data {
    void __iomem *base;
    spinlock_t lock;
    struct clk_hw *mux_hw;
};

static int ep_mux_probe(struct platform_device *pdev)
{
    struct device *dev = &pdev->dev;
    struct ep_mux_demo_data *data;

    data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
    if (!data)
        return -ENOMEM;

    spin_lock_init(&data->lock);

    data->base = devm_platform_ioremap_resource(pdev, 0);
    if (IS_ERR(data->base))
        return PTR_ERR(data->base);

    /* bit 0 of the mux register selects between the two parents above */
    data->mux_hw = devm_clk_hw_register_mux(dev, "ep_mux_out",
                                             ep_mux_parents,
                                             ARRAY_SIZE(ep_mux_parents),
                                             0, data->base, 0, 1, 0, &data->lock);
    if (IS_ERR(data->mux_hw))
        return PTR_ERR(data->mux_hw);

    return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, data->mux_hw);
}

static const struct of_device_id ep_mux_of_match[] = {
    { .compatible = "ep,clk-mux-demo" },
    { }
};
MODULE_DEVICE_TABLE(of, ep_mux_of_match);

static struct platform_driver ep_mux_driver = {
    .probe = ep_mux_probe,
    .driver = {
        .name = "ep_clk_mux_demo",
        .of_match_table = ep_mux_of_match,
    },
};
module_platform_driver(ep_mux_driver);

MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("EmbeddedPathashala mux clock demo");

Matching device tree node:

ep_mux_ctrl: clock-controller@8000 {
    compatible = "ep,clk-mux-demo";
    reg = <0x8000 0x4>;
    #clock-cells = <0>;
    clocks = <&ep_bus_clk>, <&ep_ext_osc>;
};

Build and Run

make -C /lib/modules/$(uname -r)/build M=$(pwd) modules
sudo insmod ep_mux_clk_demo.ko
cat /sys/kernel/debug/clk/clk_summary | grep -A2 ep_mux_out

Expected clk_summary excerpt, showing which of the two parents is currently active:

ep_mux_out                1        1        0   100000000          0

Registering a Read-Only Mux Variant

Some SoCs preconfigure a mux at reset and never allow software to change it. Only the
clk_mux_flags argument changes to express this:

data->mux_hw = devm_clk_hw_register_mux(dev, "ep_mux_readonly",
                                         ep_mux_parents,
                                         ARRAY_SIZE(ep_mux_parents),
                                         0, data->base, 0, 1,
                                         CLK_MUX_READ_ONLY, &data->lock);

The framework automatically assigns clk_mux_ro_ops instead of
clk_mux_ops in this case, so any attempt to call
clk_set_parent() against it will simply have no effect — there is no
set_parent callback for the CCF to call at all.

Switchable vs Read-Only Mux Clocks

Common Mistakes

Best Practices

Summary and Key Takeaways

Frequently Asked Questions

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