Introduction

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How a Peripheral Generates One Interrupt Line

A complex peripheral like USART can trigger an interrupt for many different reasons — received data, transmitted data, errors, idle line, CTS changes. Yet the NVIC receives only one IRQ signal per peripheral. The peripheral’s internal logic combines all its individual event flags into a single interrupt output using an OR-gate network controlled by enable bits.

Understanding this mapping is essential: the ISR must read the peripheral’s status register to determine which event(s) fired, because the NVIC cannot tell you which internal flag caused the interrupt — it only knows that the peripheral’s IRQ line is asserted.

Why your ISR must check SR explicitly

/* USART2 ISR — must check every possible flag, not just assume RXNE */
void USART2_IRQHandler(void)
{
    uint32_t sr = USART2->SR;
    uint32_t cr1 = USART2->CR1;

    /* Check RXNE first — most common event */
    if ((sr & USART_SR_RXNE) && (cr1 & USART_CR1_RXNEIE)) {
        uint8_t byte = (uint8_t)USART2->DR;   /* reading DR clears RXNE */
        rx_buffer_put(byte);
    }

    /* Check overrun — also asserted via RXNEIE path */
    else if ((sr & USART_SR_ORE) && (cr1 & USART_CR1_RXNEIE)) {
        (void)USART2->SR;   /* read SR then DR to clear ORE */
        (void)USART2->DR;
        overrun_error_count++;
    }

    /* Transmit complete */
    if ((sr & USART_SR_TC) && (cr1 & USART_CR1_TCIE)) {
        USART2->CR1 &= ~USART_CR1_TCIE;   /* disable TC interrupt */
        tx_complete_callback();
    }
}

NVIC Interrupt Set-Pending Registers (ISPR)

The Interrupt Set-Pending Registers (NVIC_ISPR0 through NVIC_ISPR7) allow software to read or force-pend any external IRQ. Each register is 32 bits wide, covering 32 consecutive IRQ lines. Writing a 1 to a bit sets that IRQ to pending state; writing 0 has no effect. Reading a bit tells you whether the IRQ is currently pending.

/* Software-trigger USART3 IRQ39 (test ISR without real hardware) */
/* IRQ39 → ISPR[1] bit 7 */
#define NVIC_ISPR1  (*(volatile uint32_t *)0xE000E204U)
NVIC_ISPR1 = (1U << 7);   /* pend USART3 IRQ */

/* Using CMSIS: */
NVIC_SetPendingIRQ(USART3_IRQn);

/* Check if IRQ39 is pending: */
bool usart3_pending(void)
{
    return (NVIC_GetPendingIRQ(USART3_IRQn) != 0);
}

/* Clear a pending IRQ (use ICPR, not ISPR): */
#define NVIC_ICPR1  (*(volatile uint32_t *)0xE000E284U)
NVIC_ICPR1 = (1U << 7);   /* clear pending USART3 */
/* CMSIS: NVIC_ClearPendingIRQ(USART3_IRQn); */

Interrupt Priority: Urgency and Priority Value

Priority = Urgency

In everyday life, priority means urgency — something with higher priority gets serviced before something with lower priority. In a Cortex-M processor, when two interrupts arrive simultaneously (or a new interrupt arrives while one is executing), the NVIC must decide which handler runs first. That decision is governed entirely by the priority assigned to each interrupt.

Priority Value = a number encoding urgency

Each IRQ and each system exception (except Reset, NMI, HardFault which are fixed) has a priority value — a number stored in the NVIC_IPR registers. The priority value quantifies urgency relative to other exceptions.

Worked example: TIMER vs ADC

• TIMER priority value (4) is less than ADC priority value (5) → TIMER interrupt is more urgent
• TIMER priority is said to be higher than ADC priority
• If both arrive simultaneously, NVIC runs TIMER ISR first
• If TIMER arrives while the ADC ISR is executing, TIMER preempts ADC (nested interrupt)
• If ADC arrives while TIMER ISR is executing, ADC stays pending until TIMER finishes

Priority Levels: The IPR Register and Vendor Implementation

The ARM Cortex-M architecture reserves an 8-bit field for each IRQ’s priority in the NVIC_IPR registers. This allows up to 256 distinct priority levels (values 0–255). However, ARM does not require all 8 bits to be implemented — chip vendors may implement only the most significant N bits, discarding the least significant bits.

NVIC Priority Registers (IPR) — Structure and Access

The NVIC contains 60 32-bit Interrupt Priority Registers (NVIC_IPR0 through NVIC_IPR59). Each 32-bit register holds priority fields for 4 consecutive IRQs, one byte per IRQ (8 bits each, though only the upper N bits are implemented).

Direct register access for any IRQ priority

/* Formula: IPR register index = IRQ_number / 4
             Byte offset within register = IRQ_number % 4
             Bit position in 32-bit word = (IRQ_number % 4) * 8 */

/* Set priority of IRQ39 (USART3) to value 5 on STM32F4 (4 bits implemented) */

/* Method 1: Direct register, 32-bit access */
#define NVIC_IPR_BASE  ((volatile uint32_t *)0xE000E400U)
uint32_t irq = 39;
uint32_t reg_idx  = irq / 4;         /* = 9 → NVIC_IPR9 */
uint32_t byte_pos = irq % 4;         /* = 3 → bits [31:24] of IPR9 */
uint32_t shift    = byte_pos * 8;    /* = 24 */

NVIC_IPR_BASE[reg_idx] &= ~(0xFFU << shift);         /* clear current priority */
NVIC_IPR_BASE[reg_idx] |= ((5U << 4) << shift);      /* write 5 (MSB-aligned) */

/* Method 2: Byte access (simpler) */
#define NVIC_IPR_BYTE ((volatile uint8_t *)0xE000E400U)
NVIC_IPR_BYTE[39] = (5U << 4);    /* 0x50 */

/* Method 3: CMSIS (recommended — handles __NVIC_PRIO_BITS automatically) */
NVIC_SetPriority(USART3_IRQn, 5);

/* Read back: */
uint32_t current = NVIC_GetPriority(USART3_IRQn);  /* returns 5 on STM32F4 */

Priority registers for system exceptions (SHPR)

System exceptions (MemManage, BusFault, UsageFault, SVC, PendSV, SysTick) use the System Handler Priority Registers (SHPR1–3) inside the SCB, not the NVIC_IPR registers. The format is identical — 8-bit fields, MSB-aligned.

/* System Handler Priority Register locations */
#define SCB_SHPR1  (*(volatile uint32_t *)0xE000ED18U)  /* MemManage/BusFault/UsageFault */
#define SCB_SHPR2  (*(volatile uint32_t *)0xE000ED1CU)  /* SVC */
#define SCB_SHPR3  (*(volatile uint32_t *)0xE000ED20U)  /* PendSV / SysTick */

/* Set SVC priority = 2 (bits 31:24 of SHPR2) */
SCB->SHP[10 - 4] = (2U << 4);   /* CMSIS index: SVCall maps to SHP[10-4]=SHP[6] */

/* CMSIS equivalents: */
NVIC_SetPriority(SVCall_IRQn, 2);
NVIC_SetPriority(PendSV_IRQn, 15);   /* lowest priority for context switch */
NVIC_SetPriority(SysTick_IRQn, 15);  /* same as PendSV */

Pre-empt Priority vs Sub-Priority

The NVIC priority field for each IRQ is further divided into two parts by the PRIGROUP setting in SCB_AIRCR. This split determines how two aspects of interrupt behaviour work:

PRIGROUP settings for STM32F4 (4 implemented bits)

/* STM32 HAL default: PRIGROUP = 4 → all 4 bits are pre-empt priority, no sub-priority */
/* This gives 16 nesting levels (0..15) and is the most common configuration */

/* Set PRIGROUP = 4 (all bits = pre-empt, none = sub) */
NVIC_SetPriorityGrouping(4);

/* Encode priority: 3 pre-empt bits, 1 sub-priority bit (PRIGROUP=1 example) */
uint32_t encoded = NVIC_EncodePriority(
    1,   /* PRIGROUP value */
    5,   /* pre-empt priority = 5 (range 0..7) */
    0    /* sub-priority = 0 (range 0..1) */
);
NVIC_SetPriority(USART3_IRQn, encoded);

/* FreeRTOS recommendation for STM32F4:
   Set configKERNEL_INTERRUPT_PRIORITY = 15 (lowest)
   Set configMAX_SYSCALL_INTERRUPT_PRIORITY = 5 (ISRs ≤ 4 cannot use FreeRTOS API)
   All priority bits = pre-empt (PRIGROUP = 4) */
#define configKERNEL_INTERRUPT_PRIORITY        (15 << 4)   /* 0xF0 */
#define configMAX_SYSCALL_INTERRUPT_PRIORITY   ( 5 << 4)   /* 0x50 */

Complete Priority Configuration Example

The following example configures four interrupts on STM32F411 with a well-reasoned priority scheme. All bits are pre-empt (PRIGROUP=4 default). Lower value = runs sooner / can preempt higher values.

#include "stm32f4xx.h"

/*  Priority scheme (STM32F4, 4-bit pre-empt, PRIGROUP=4):
    0  → Reset (fixed –3, not configurable)
    1  → NMI   (fixed –2, not configurable)
    2  → Hard  (fixed –1, not configurable)
    ─────────────────────────────────────────
    3  → (reserved for future critical use)
    4  → TIM6 (DAC underrun alarm) — most urgent user ISR
    5  → USART1 (high-speed data)
    6  → USART3 (lower-speed data)
    7  → ADC   (periodic sample)
    …
    15 → PendSV / SysTick (RTOS scheduler — lowest)   */

void priority_init(void)
{
    /* PRIGROUP = 4: all 4 bits = pre-empt, no sub-priority */
    NVIC_SetPriorityGrouping(4);

    /* System exceptions */
    NVIC_SetPriority(SVCall_IRQn,   3);
    NVIC_SetPriority(PendSV_IRQn,  15);
    NVIC_SetPriority(SysTick_IRQn, 15);

    /* Peripheral IRQs */
    NVIC_SetPriority(TIM6_DAC_IRQn, 4);
    NVIC_SetPriority(USART1_IRQn,   5);
    NVIC_SetPriority(USART3_IRQn,   6);
    NVIC_SetPriority(ADC_IRQn,      7);

    /* Enable all */
    NVIC_EnableIRQ(TIM6_DAC_IRQn);
    NVIC_EnableIRQ(USART1_IRQn);
    NVIC_EnableIRQ(USART3_IRQn);
    NVIC_EnableIRQ(ADC_IRQn);
}

/* Verification: read back all priorities */
void priority_verify(void)
{
    /* These should print 4, 5, 6, 7 on STM32F4 */
    uint32_t t = NVIC_GetPriority(TIM6_DAC_IRQn);   /* = 4 */
    uint32_t u1 = NVIC_GetPriority(USART1_IRQn);     /* = 5 */
    uint32_t u3 = NVIC_GetPriority(USART3_IRQn);     /* = 6 */
    uint32_t a = NVIC_GetPriority(ADC_IRQn);         /* = 7 */
    (void)t; (void)u1; (void)u3; (void)a;
}

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