1. What is CMSIS?

CMSIS (Cortex Microcontroller Software Interface Standard) is an ARM-defined hardware abstraction layer for Cortex-M processors. It provides:

• CMSIS-Core: Peripheral register structs (SCB, NVIC, SysTick), intrinsic functions, and core access functions
• CMSIS-DSP: Optimized DSP/ML algorithms for Cortex-M4 FPU
• CMSIS-RTOS: Standard RTOS API (wrapper over FreeRTOS, Mbed, etc.)
• CMSIS-Driver: Peripheral driver interface (UART, SPI, I2C…)

For this tutorial, we focus on CMSIS-Core which maps to the header file core_cm4.h included via stm32f4xx.h.

2. CMSIS SysTick Configuration

SysTick_Config(uint32_t ticks) is a CMSIS function that fully configures SysTick with one call. It sets the reload value, enables the interrupt, and enables the counter.

void init_systick_timer(uint32_t tick_hz)
{
    uint32_t *pSRVR =
        (uint32_t*)0xE000E014;
    uint32_t *pSCSR =
        (uint32_t*)0xE000E010;

    uint32_t count =
        (SYSTICK_TIM_CLK/tick_hz)-1;

    *pSRVR &= ~(0x00FFFFFF);
    *pSRVR |= count;

    *pSCSR |= (1 << 1); /* TICKINT */
    *pSCSR |= (1 << 2); /* CLKSRC  */
    *pSCSR |= (1 << 0); /* ENABLE  */
}

void init_systick_timer(uint32_t tick_hz)
{
    uint32_t ticks =
        (SYSTICK_TIM_CLK/tick_hz)-1;

    /* SysTick_Config sets:
       SYST_RVR = ticks
       SYST_CVR = 0 (clear)
       SYST_CSR: TICKINT=1,
                 CLKSOURCE=1,
                 ENABLE=1         */
    SysTick_Config(ticks);
}

SysTick_Config Implementation (from CMSIS source)

/* CMSIS SysTick_Config — for reference (do not copy verbatim) */
/* Source: ARM CMSIS 5, core_cm4.h */
static inline uint32_t SysTick_Config(uint32_t ticks)
{
    /* Reload value must fit in 24 bits (SysTick is 24-bit) */
    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
        return 1UL;  /* error: ticks too large */

    SysTick->LOAD = ticks - 1UL;  /* Set reload value */

    /* Set SysTick exception priority to lowest */
    NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL);

    SysTick->VAL  = 0UL;  /* Clear current value */

    /* Enable: CLKSOURCE=1 (processor clock), TICKINT=1, ENABLE=1 */
    SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
                    SysTick_CTRL_TICKINT_Msk   |
                    SysTick_CTRL_ENABLE_Msk;
    return 0UL;  /* success */
}

3. CMSIS SCB Structure — System Control Block

CMSIS defines SCB as a global pointer to a SCB_Type struct at address 0xE000ED00. All SCB registers are accessible as struct fields with descriptive names.

CMSIS SHCSR Masks

4. Complete Side-by-Side Comparison

/* Enable fault handlers */
uint32_t *pSHCSR =
    (uint32_t*)0xE000ED24;
*pSHCSR |= (1 << 16);
*pSHCSR |= (1 << 17);
*pSHCSR |= (1 << 18);

/* Enable fault handlers */
SCB->SHCSR |=
    SCB_SHCSR_MEMFAULTENA_Msk;
SCB->SHCSR |=
    SCB_SHCSR_BUSFAULTENA_Msk;
SCB->SHCSR |=
    SCB_SHCSR_USGFAULTENA_Msk;

__attribute__((naked))
void init_scheduler_stack(
    uint32_t top)
{
    __asm volatile(
        "MSR MSP, %0" :: "r"(top));
    __asm volatile("BX LR");
}

__attribute__((naked))
void init_scheduler_stack(
    uint32_t top)
{
    /* __set_MSP is a CMSIS
       intrinsic function       */
    __set_MSP(top);
    __asm volatile("BX LR");
}

void schedule(void)
{
    uint32_t *pICSR =
        (uint32_t*)0xE000ED04;
    *pICSR |= (1 << 28);
}

void schedule(void)
{
    SCB->ICSR |=
        SCB_ICSR_PENDSVSET_Msk;
}

5. CMSIS Core Intrinsic Functions

CMSIS-Core provides inline assembly wrappers for common Cortex-M core operations. These compile to the exact same instructions as hand-written assembly, but are portable and self-documenting.

6. Complete CMSIS Scheduler

/* ================================================================
 * CMSIS TASK SCHEDULER
 * Same architecture as Example 15 but using CMSIS abstractions
 * ================================================================ */
#include <stdio.h>
#include "main.h"
#include "stm32f4xx.h"  /* Includes core_cm4.h → CMSIS definitions */

typedef struct {
    uint32_t psp_value;
    uint32_t block_count;
    uint8_t  current_state;
    void     (*task_handler)(void);
} TCB_t;

TCB_t    user_tasks[MAX_TASKS];
uint8_t  current_task = 1;
uint32_t g_tick_count  = 0;

int main(void)
{
    /* ── 1. Enable configurable fault handlers via CMSIS ── */
    SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
    SCB->SHCSR |= SCB_SHCSR_BUSFAULTENA_Msk;
    SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk;

    /* ── 2. Move MSP to scheduler stack area ── */
    init_scheduler_stack(SCHED_STACK_START);

    /* ── 3. Build fake context frames for all tasks ── */
    init_tasks_stack();

    /* ── 4. Init LEDs ── */
    led_init_all();

    /* ── 5. Configure SysTick at 1kHz using CMSIS ── */
    init_systick_timer(TICK_HZ);

    /* ── 6. Switch to PSP for Thread mode ── */
    switch_sp_to_psp();

    /* ── 7. Launch Task1 ── */
    task1_handler();

    for(;;);
}

/* ── CMSIS SysTick setup ── */
void init_systick_timer(uint32_t tick_hz)
{
    uint32_t ticks = (SYSTICK_TIM_CLK / tick_hz) - 1;
    SysTick_Config(ticks);  /* CMSIS: sets RVR, clears CVR, enables all */
}

/* ── CMSIS __set_MSP instead of inline asm ── */
__attribute__((naked)) void init_scheduler_stack(uint32_t top)
{
    __set_MSP(top);  /* CMSIS intrinsic: MSR MSP, R0 */
    __asm volatile("BX LR");
}

/* ── Enable processor faults using CMSIS SCB struct ── */
void enable_processor_faults(void)
{
    SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;  /* bit 16 */
    SCB->SHCSR |= SCB_SHCSR_BUSFAULTENA_Msk;  /* bit 17 */
    SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk;  /* bit 18 */
}

/* ── Pend PendSV using CMSIS SCB->ICSR ── */
void schedule(void)
{
    SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;  /* bit 28 */
}

/* ── SysTick Handler: tick + unblock + pend PendSV via CMSIS ── */
void SysTick_Handler(void)
{
    update_global_tick_count();
    unblock_tasks();
    SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;  /* trigger context switch */
}

/* ── PendSV: identical to Example 15 (no CMSIS equiv for STMDB/LDMIA) ── */
__attribute__((naked)) void PendSV_Handler(void)
{
    __asm volatile("MRS R0, PSP");
    __asm volatile("STMDB R0!, {R4-R11}");
    __asm volatile("PUSH {LR}");
    __asm volatile("BL save_psp_value");
    __asm volatile("BL update_next_task");
    __asm volatile("BL get_psp_value");
    __asm volatile("LDMIA R0!, {R4-R11}");
    __asm volatile("MSR PSP, R0");
    __asm volatile("POP {LR}");
    __asm volatile("BX LR");
}

/* ── Task handlers use task_delay (blocking) instead of busy-wait ── */
void task1_handler(void)
{
    while(1) {
        led_on(LED_GREEN);
        task_delay(1000);   /* block for 1000ms */
        led_off(LED_GREEN);
        task_delay(1000);
    }
}

void task2_handler(void)
{
    while(1) {
        led_on(LED_ORANGE);
        task_delay(500);    /* block for 500ms */
        led_off(LED_ORANGE);
        task_delay(500);
    }
}

/* ── task_delay uses CMSIS __disable_irq / __enable_irq ── */
void task_delay(uint32_t ticks)
{
    __disable_irq();  /* CPSID I = PRIMASK=1 */
    if (current_task != 0) {
        user_tasks[current_task].block_count =
            g_tick_count + ticks;
        user_tasks[current_task].current_state = TASK_BLOCKED_STATE;
        schedule();
    }
    __enable_irq();   /* CPSIE I = PRIMASK=0 */
}

7. CMSIS SysTick_Type Struct — Behind the Scenes

/* CMSIS SysTick_Type definition (from core_cm4.h — ARM copyright) */
/* Structure at base address 0xE000E010 */
typedef struct
{
    volatile uint32_t CTRL;   /* 0xE000E010: Control and Status Register */
    volatile uint32_t LOAD;   /* 0xE000E014: Reload Value Register */
    volatile uint32_t VAL;    /* 0xE000E018: Current Value Register */
    volatile uint32_t CALIB;  /* 0xE000E01C: Calibration Register (RO) */
} SysTick_Type;

#define SysTick  ((SysTick_Type *)0xE000E010)

/* Bit masks for SysTick->CTRL */
#define SysTick_CTRL_ENABLE_Msk     (1UL << 0)  /* Counter enable */
#define SysTick_CTRL_TICKINT_Msk    (1UL << 1)  /* Enable exception */
#define SysTick_CTRL_CLKSOURCE_Msk  (1UL << 2)  /* Clock: 1=processor */
#define SysTick_CTRL_COUNTFLAG_Msk  (1UL << 16) /* Count reached zero */
#define SysTick_LOAD_RELOAD_Msk     (0xFFFFFF)  /* 24-bit mask */

8. NVIC Functions in CMSIS

9. Interview Questions & Answers