IPR Vendor Implementation

The ARM Cortex-M architecture specifies 60 Interrupt Priority Registers (IPR0–IPR59), each 32 bits wide. Every 8-bit field inside those registers holds the priority for one IRQ:

Each 8-bit field is architecturally defined, but MCU vendors do not implement all 8 bits. They implement only the most-significant N bits and leave the lower bits as read-as-zero / write-ignored:

Priority Levels Visualised

The ARM exception model defines a continuous priority number line from very negative (highest priority, fixed) to 0xFF (lowest programmable priority):

With a 3-bit implementation, programmable exceptions can only occupy 8 slots (0x00, 0x20, 0x40, … 0xE0). With 4 bits they occupy 16 slots (0x00 to 0xF0 in steps of 0x10). The lower bits are always ignored by hardware.

SHPR: System Exception Priorities

External IRQs use NVIC_IPR registers. But the configurable system exceptions (MemManage, BusFault, UsageFault, SVC, DebugMonitor, PendSV, SysTick) use a separate set of registers inside the System Control Block:

/* CMSIS — set SysTick to priority 15, PendSV to priority 14 */
NVIC_SetPriority(SysTick_IRQn, 15);   /* writes SHPR3 byte [31:24] */
NVIC_SetPriority(PendSV_IRQn,  14);   /* writes SHPR3 byte [23:16] */

/* Direct register access for STM32F4 (4-bit, top nibble) */
SCB->SHP[11] = (15U << 4);  /* SysTick  — SHP index 11 */
SCB->SHP[10] = (14U << 4);  /* PendSV   — SHP index 10 */
SCB->SHP[ 7] = ( 5U << 4);  /* SVC      — SHP index 7  */

Pre-empt vs Sub-Priority

ARM divides each interrupt’s priority field into two sub-fields:

Priority Grouping (PRIGROUP)

The PRIGROUP field (bits [10:8]) in the Application Interrupt and Reset Control Register (AIRCR, address 0xE000ED0C) controls how the implemented priority bits are divided between pre-empt priority and sub-priority:

The PRIGROUP value selects the split point within the 8-bit priority field. The ARM spec defines the split in terms of the 8-bit field, but only the implemented bits matter:

/* Set PRIGROUP = 4 (FreeRTOS default — all bits are pre-empt) */
SCB->AIRCR = (0x05FAU << 16) | (4U << 8);

/* CMSIS equivalent */
NVIC_SetPriorityGrouping(4U);

/* Verify */
uint32_t pg = NVIC_GetPriorityGrouping();  /* should return 4 */

Worked Case Studies

Case 1: PRIGROUP = 0 (default), 3-bit MCU

With PRIGROUP = 0 the architecture says the pre-empt field occupies bits [7:1] (7 bits) and the sub-priority field occupies bit [0] (1 bit). However, the MCU only implements the top 3 bits (bits [7:5]).

Case 2: PRIGROUP = 4, 4-bit MCU (STM32F4 + FreeRTOS)

FreeRTOS requires PRIGROUP = 4 so that all implemented bits are pre-empt bits and there are zero sub-priority bits. This is mandatory because FreeRTOS’s taskENTER_CRITICAL() uses the BASEPRI register, which compares only pre-empt priority — sub-priority is irrelevant and must not exist.

Case 3: PRIGROUP = 5, 4-bit MCU

PRIGROUP = 5 splits at bit 6: pre-empt = bits [7:6], sub = bits [5:0]. With 4 bits implemented ([7:4]):

• Pre-empt: bits [7:6] — 2 bits implemented → 4 pre-empt levels (0, 1, 2, 3)
• Sub-priority: bits [5:4] of the implemented region — 2 bits → 4 sub-priority levels

This is sometimes used in bare-metal systems where you want a coarse nesting hierarchy but fine-grained ordering within each tier.

Practical Code

Reading the Priority of an Active ISR

#include "stm32f4xx.h"

/* Return the raw 8-bit IPR byte for any IRQn (including system exceptions) */
uint8_t get_raw_priority(IRQn_Type irq)
{
    if (irq >= 0) {
        /* External IRQ: NVIC_IPR byte array */
        return NVIC->IP[(uint32_t)irq];
    } else {
        /* System exception: SCB->SHP[] */
        /* SHP index = irq + 16 - 4 (SHP starts at exception 4) */
        return SCB->SHP[(uint32_t)(irq & 0xF) - 4];
    }
}

/* Return the logical priority level (right-aligned) for STM32F4 (4-bit) */
uint32_t get_logical_priority(IRQn_Type irq)
{
    return get_raw_priority(irq) >> 4;
}

Configuring PRIGROUP + Priorities (Bare Metal)

#include "stm32f4xx.h"

void nvic_priority_init(void)
{
    /*
     * Step 1: Set PRIGROUP = 4
     *   All 4 implemented bits are pre-empt priority.
     *   Zero sub-priority levels.
     */
    NVIC_SetPriorityGrouping(4U);

    /*
     * Step 2: Assign priorities.
     *   NVIC_SetPriority() takes the logical (right-aligned) value;
     *   CMSIS shifts it left by (8 - __NVIC_PRIO_BITS) internally.
     *   On STM32F4, __NVIC_PRIO_BITS = 4, so shift = 4.
     */
    NVIC_SetPriority(USART3_IRQn, 5);   /* 0x50 in IPR */
    NVIC_SetPriority(TIM2_IRQn,   3);   /* 0x30 in IPR — higher urgency */
    NVIC_SetPriority(ADC_IRQn,    7);   /* 0x70 in IPR — lower urgency  */

    /* System exceptions */
    NVIC_SetPriority(SysTick_IRQn, 15); /* 0xF0 in SHPR3 — lowest */
    NVIC_SetPriority(PendSV_IRQn,  15); /* 0xF0 in SHPR3 — lowest */
    NVIC_SetPriority(SVCall_IRQn,  15); /* 0xF0 in SHPR2 */
}

FreeRTOS Priority Constants Explained

/*
 * FreeRTOS uses PRIGROUP=4 on STM32F4 (4 implemented pre-empt bits = 16 levels).
 * Logical priority 15 → raw 0xF0 (lowest).
 * Logical priority  0 → raw 0x00 (highest, same as HardFault range — avoid!).
 *
 * configKERNEL_INTERRUPT_PRIORITY:
 *   The tick (SysTick) and yield (PendSV) use the LOWEST priority.
 *   This ensures every application ISR can pre-empt the RTOS tick.
 *
 * configMAX_SYSCALL_INTERRUPT_PRIORITY:
 *   ISRs that call FreeRTOS API functions (e.g. xQueueSendFromISR) must have
 *   a priority NUMERICALLY GREATER THAN OR EQUAL TO this value (i.e. lower urgency).
 *   ISRs with priority LOWER VALUE than this cannot call any FreeRTOS API.
 */

#define configKERNEL_INTERRUPT_PRIORITY      (15 << 4)  /* 0xF0 */
#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( 5 << 4)  /* 0x50 */

/*
 * Safe zone: priorities 5–15 (raw 0x50–0xF0) can call FreeRTOS API.
 * Unsafe zone: priorities 0–4 (raw 0x00–0x40) CANNOT call FreeRTOS API.
 *
 * taskENTER_CRITICAL() sets BASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY.
 * This masks all interrupts with priority value >= 0x50 but allows those
 * with priority value < 0x50 (i.e. higher urgency) to still fire.
 */

Verifying IPR Values at Runtime

/* Debug helper: dump first 16 IRQ priorities over SWO/UART */
void dump_nvic_priorities(void)
{
    uint32_t pg = NVIC_GetPriorityGrouping();
    uint32_t pre_bits  = 7U - pg;   /* approximate for fully-implemented field */
    (void)pre_bits;

    for (int i = 0; i < 16; i++) {
        uint32_t raw     = NVIC->IP[i];
        uint32_t logical = raw >> (8 - __NVIC_PRIO_BITS);  /* right-align */
        printf("IRQ%2d: raw=0x%02X  logical=%lu\r\n", i, raw, logical);
    }
}

Frequently Asked Questions

Suggested Diagrams for This Lecture

• IPR register layout: 4×8-bit fields per 32-bit word, annotated with IRQ indices
• 8-bit priority byte with top N bits highlighted (implemented) vs lower bits greyed out
• PRIGROUP split visualisation for all 8 settings on a 4-bit MCU
• AIRCR register bit-field layout with PRIGROUP highlighted at bits [10:8]
• FreeRTOS priority zones: safe (5–15) vs forbidden (0–4) on STM32F4